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general description the ds12885, ds12887, and ds12c887 real-timeclocks (rtcs) are designed to be direct replacements for the ds1285 and ds1287. the devices provide a real-time clock/calendar, one time-of-day alarm, three maskable interrupts with a common interrupt output, a programmable square wave, and 114 bytes of battery- backed static ram (113 bytes in the ds12c887 and ds12c887a). the ds12887 integrates a quartz crystal and lithium energy source into a 24-pin encapsulated dip package. the ds12c887 adds a century byte at address 32h. for all devices, the date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. the devices also operate in either 24-hour or 12-hour format with an am/pm indicator. a precision temperature-compensated circuit monitors the status of v cc . if a primary power failure is detected, the device automatically switches to a backup supply. a lithiumcoin-cell battery can be connected to the v bat input pin on the ds12885 to maintain time and date operationwhen primary power is absent. the device is accessed through a multiplexed byte-wide interface, which sup- ports both intel and motorola modes. applications embedded systemsutility meters security systems network hubs, bridges, and routers features ? drop-in replacement for ibm at computer clock/calendar ? rtc counts seconds, minutes, hours, day, date, month, and year with leap year compensation through 2099 ? binary or bcd time representation ? 12-hour or 24-hour clock with am and pm in 12-hour mode ? daylight saving time option ? selectable intel or motorola bus timing ? interfaced with software as 128 ram locations ? 14 bytes of clock and control registers ? 114 bytes of general-purpose, battery-backed ram (113 bytes in the ds12c887 and ds12c887a) ? ram clear function (ds12885, ds12887a, and ds12c887a) ? interrupt output with three independently maskable interrupt flags ? time-of-day alarm once per second to once per day ? periodic rates from 122s to 500ms ? end-of-clock update cycle flag ? programmable square-wave output ? automatic power-fail detect and switch circuitry ? optional 28-pin plcc surface mount package or 32-pin tqfp (ds12885) ? optional encapsulated dip (edip) package with integrated crystal and battery (ds12887, ds12887a, ds12c887, ds12c887a) ? optional industrial temperature range available ? underwriters laboratory (ul) recognized ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ______________________________________________ maxim integrated products 1 ds12885 ds83c520 r/w as gnd x2 x1 v cc v cc crystal ds v bat ad(0?) sqw reset irq rclr csmot typical operating circuit 19-5213; rev 4; 4/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations and ordering information appear at end of data sheet. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 2 __________________________________________________ ___________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc pin relative to ground .....-0.3v to +6.0v operating temperature range ................................................... commercial (noncondensing) .............................0? to +70? operating temperature range ................................................... industrial (noncondensing)...............................-40? to +85? storage temperature range edip ..................................................................-40? to +85? pdip, so, plcc, tqfp ..................................-55? to +125? lead temperature (soldering, 10s) .................................+260? ( note: edip is hand or wave-soldered only.) soldering temperature (reflow) pdip, so, plcc............................................................+260? tqfp .............................................................................+245? dc electrical characteristics ( v cc = +4.5v to +5.5v , t a = over the operating range, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units supply voltage v cc (note 3) 4.5 5.5 v v bat input voltage v bat (note 3) 2.5 4.0 v input logic 1 v ih (note 3) 2.2 v cc + 0.3 v input logic 0 v il (note 3) -0.3 +0.8 v v cc power-supply current i cc1 (note 4) 15 ma v cc standby current i ccs (note 5) ma input leakage i il -1.0 +1.0 ? i/o leakage i ol (note 6) -1.0 +1.0 ? input current i mot (note 7) -1.0 +500 ? output at 2.4v i oh (note 3) -1.0 ma output at 0.4v i ol (note 3) 4.0 ma power-fail voltage v pf (note 3) 4.0 4.25 4.5 v vrt trip point vrt trip 1.3 v downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ __________________ 3 dc electrical characteristics ( v cc = 0v, v bat = 3.0v , t a = over the operating range, unless otherwise noted.) (note 2) parameter symbol conditions min typ max units v bat current (osc on); t a = +25?, v backup = 3.0v i bat (note 8) 500 na v bat current (oscillator off) i batdr (note 8) 100 na ac electrical characteristics ( v cc = 4.5v to 5.5v , t a = over the operating range.) (note 2) parameter symbol conditions min typ max units cycle time t cyc 385 dc ns pulse width, ds low or r/ w high pw el 150 ns pulse width, ds high or r/ w low pw eh 125 ns input rise and fall t r , t f 30 ns r/ w hold time t rwh 10 ns r/ w setup time before ds/e t rws 50 ns chip-select setup time beforeds or r/ w t cs 20 ns chip-select hold time t ch 0n s read-data hold time t dhr 10 80 ns write-data hold time t dhw 0n s address valid time to as fall t asl 30 ns address hold time to as fall t ahl 10 ns delay time ds/e to as rise t asd 20 ns pulse width as high pw ash 60 ns delay time, as to ds/e rise t ased 40 ns output data delay time from dsor r/ w t ddr 20 120 ns data setup time t dsw 100 ns reset pulse width t rwl 5 s irq release from ds t irds 2 s irq release from reset t irr 2 s downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 4 __________________________________________________ ___________________ pw ash pw el t ased t cyc t rws t cs t rwh t ch pw eh t asd ad0?d7 read cs r/ w asds ad0?d7 write t dhw t dhr t ddr t ahl t asl t dsw motorola bus read/write timing intel bus write timing pw ash pw el pw eh t cs t ahl t asl t dsw t dhw t ch t asd t asd t cyc cs r/w asds ad0?d7 write t ased downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ __________________ 5 t cs t ahl t asl t cyc pw ash pw el pw eh cs r/w asds ad0?d7 t asd t asd t ased t ddr t dhr t ch intel bus read timing t rwl t irr t irds ds reset irq irq release delay timing outputs inputs high-z don't care valid recognized recognized valid v cc t f v pf(max) v pf(min) t rpu t r t dr power-up/power-down timing downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 6 __________________________________________________ ___________________ power-up/power-down characteristics (t a = -40? to +85?) (note 2) parameter symbol conditions min typ max units recovery at power-up t rpu 20 200 ms v cc fall time; v pf(max) to v pf(min) t f 300 ? v cc rise time; v pf(min) to v pf(max) t r 0 s capacitance (t a = +25?) (note 9) parameter symbol conditions min typ max units capacitance on all input pinsexcept x1 and x2 c in 5p f capacitance on irq , sqw, and dq pins c io 7p f data retention (t a = +25?) parameter symbol conditions min typ max units expected data retention t dr 10 years ac test conditions parameter test conditions input pulse levels 0 to 3.0v output load including scope and jig 50pf + 1ttl gate input and output timing measurement reference levels input/output: v il maximum and v ih minimum input-pulse rise and fall times 5ns warning: negative undershoots below -0.3v while the part is in batte ry-backed mode may cause loss of data. note 1: rtc modules can be successfully processed through conventional wave-soldering techniques as long as temperatureexposure to the lithium energy source contained within does not exceed +85?. however, post-solder cleaning with water- washing techniques is acceptable, provided that ultrasonic vibrations are not used to prevent crystal damage. note 2: limits at -40? are guaranteed by design and not production tested. note 3: all voltages are referenced to ground. note 4: all outputs are open. note 5: specified with cs = ds = r/ w = reset = v cc ; mot, as, ad0?d7 = 0; v backup open. note 6: applies to the ad0 to ad7 pins, the irq pin, and the sqw pin when each is in a high-impedance state. note 7: the mot pin has an internal 20k pulldown. note 8: measured with a 32.768khz crystal attached to x1 and x2. note 9: guaranteed by design. not production tested. note 10: measured with a 50pf capacitance load. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks _____________________________________________________________________ 7 typical operating characteristics (v cc = +5.0v, t a = +25?, unless otherwise noted.) oscillator frequency vs. v cc ds12885 toc02 v cc (v) frequency (hz) 5.3 5.0 4.8 32768.10 32768.20 32768.30 32768.40 32768.50 32768.60 32768.7032768.00 4.5 5.5 i bat1 vs. v bat vs. temperature ds12885 toc01 v bat (v) i bat (na) 3.8 2.8 3.0 3.3 3.5 200 300 250 150 2.5 4.0 v cc = 0v +85 c +25 c 0 c -40 c +70 c +40 c power control gnd osc bus interface v cc x1x2 reset csds as r/w mot ad0?d7 divide by 8 divide by 64 divide by 64 16:1 mux square- wave generator registers a, b, c, d clock/calendar and alarm registers user ram 114 bytes clock/calendar update logic irq sqw irq generator buffered clock/ calendar and alarm registers v bat rlcr ds12885 functional diagram downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 8 __________________________________________________ ___________________ pin description pin so, pdip edip plcc tqfp name function 1 1 2 29 mot motorola or intel bus timing selector. this pin selects one of two bus types. whenconnected to v cc , motorola bus timing is selected. when connected to gnd or left disconnected, intel bus timing is selected. the pin has an internal pulldownresistor. 23 3 0x 1 34 3 1x 2 connections for standard 32.768khz quartz crystal. the internal oscillatorcircuitry is designed for operation with a crystal having a 6pf specified load capacitance (c l ). pin x1 is the input to the oscillator and can optionally be connected to an external 32.768khz oscillator. the output of the internal oscillator,pin x2, is left unconnected if an external oscillator is connected to pin x1. 4?1 4?1 5?0, 12, 14 1, 2, 3,5, 7, 8, 9, 11 ad0 ad7 multiplexed, bidirectional address/data bus. the addresses are presented during the first portion of the bus cycle and latched into the device by the falling edge of as. write data is latched by the falling edge of ds (motorola timing) or the rising edge of r/ w (intel timing). in a read cycle, the device outputs data during the latter portion of ds (ds and r/ w high for motorola timing, ds low and r/ w high for intel timing). the read cycle is terminated and the bus returns to a high-impedance state as ds transitions low in the case of motorola timing or as ds transitions high in the case of intel timing. 12, 16 12 15, 20 12, 17 gnd ground 13 13 16 13 cs active-low chip-select input. the chip-select signal must be asserted low for abus cycle in the device to be accessed. cs must be kept in the active state during ds and as for motorola timing and during ds and r/ w for intel timing. bus cycles that take place without asserting cs will latch addresses, but no access occurs. when v cc is below v pf volts, the device inhibits access by internally disabling the cs input. this action protects the rtc data and the ram data during power outages. 14 14 17 14 as address strobe input. a positive-going address-strobe pulse serves todemultiplex the bus. the falling edge of as causes the address to be latched within the device. the next rising edge that occurs on the as bus clears the address regardless of whether cs is asserted. an address strobe must immediately precede each write or read access. if a write or read is performedwith cs deasserted, another address strobe must be performed prior to a read or write access with cs asserted. 15 15 19 16 r/ w read/write input. the r/ w pin has two modes of operation. when the mot pin is connected to v cc for motorola timing, r/ w is at a level that indicates whether the current cycle is a read or write. a read cycle is indicated with a high level on r/ w while ds is high. a write cycle is indicated when r/ w is low during ds. when the mot pin is connected to gnd for intel timing, the r/ w signal is an active-low signal. in this mode, the r/ w pin operates in a similar fashion as the write-enable signal ( we ) on generic rams. data are latched on the rising edge of the signal. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a pin description (continued) pin so, pdip edip plcc tqfp name function 22 2, 3, 16, 20, 21, 22 1, 11, 13, 18, 26 4, 6, 10, 15, 20,23, 25, 27, 32 n.c. no connection. this pin should remain unconnected. pin 21 is rclr for the ds12887a/ds12c887a. on the edip, these pins are missing by design. 17 17 21 18 ds d ata s tr ob e or read inp ut. the d s p i n has tw o m od es of op er ati on d ep end i ng on the l evel of the m o t p i n. w hen the m o t p i n i s connected to v c c , m otor ol a b us ti m i ng i s sel ected . in thi s m od e, d s i s a p osi ti ve p ul se d ur i ng the l atter p or ti on of the b us cycl e and i s cal l ed d ata str ob e. d ur i ng r ead cycl es, d s si g ni fi es the ti m e that the device i s to d r i ve the b i d i r ecti onal b us. in w r i te cycl es, the tr ai l i ng ed g e of d s causes the device to l atch the w r i tten d ata. w hen the m o t p i n i s connected to gn d , intel b us ti m i ng i s sel ected . d s i d enti fi es the ti m e p er i od w hen the device d r i ves the b us w i th r ead d ata. in thi s m od e, the d s p i n op er ates i n a si m i l ar fashi on as the outp ut- enab l e ( o e ) si g nal on a g ener i c ram . 18 18 22 19 reset active-low reset input. the reset pin has no effect on the clock, calendar, or ram. on power-up, the reset pin can be held low for a time to allow the power supply to stabilize. the amount of time that reset is held low is dependent on the application. however, if reset is used on power-up, the time reset is low should exceed 200ms to ensure that the internal timer that controls the device on power-up has timed out. when reset is low and v cc is above v pf , the following occurs: a. periodic interrupt-enable (pie) bit is cleared to 0. b. alarm interrupt-enable (aie) bit is cleared to 0. c. update-ended interrupt-enable (uie) bit is cleared to 0. d. periodic-interrupt flag (pf) bit is cleared to 0. e. alarm-interrupt flag (af) bit is cleared to 0. f. update-ended interrupt flag (uf) bit is cleared to 0. g. interrupt-request status flag (irqf) bit is cleared to 0. h. irq pin is in the high-impedance state. i. the device is not accessible until reset is returned high. j. square-wave output-enable (sqwe) bit is cleared to 0.in a typical application, reset can be connected to v cc . this connection allows the device to go in and out of power fail without affecting any of the controlregisters. real-time clocks ___________________________________________________ __________________ 9 downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 10 _________________________________________________ ___________________ pin description (continued) pin so, pdip edip plcc tqfp name function 19 19 23 21 irq active-low interrupt request output. the irq pin is an active-low output of the device that can be used as an interrupt input to a processor. the irq output remains low as long as the status bit causing the interrupt is present and thecorresponding interrupt-enable bit is set. the processor program normally reads the c register to clear the irq pin. the reset pin also clears pending interrupts. when no interrupt conditions are present, the irq level is in the high- impedance state. multiple interrupting devices can be connected to an irq bus, provided that they are all open drain. the irq pin is an open-drain output and requires an external pullup resistor to v cc . 20 24 22 v bat connection for a primary battery. (ds12885 only.) battery voltage must be heldbetween the minimum and maximum limits for proper operation. if a backup supply is not supplied, v bat must be grounded. connect the battery directly to the v bat pin. diodes in series between the v bat pin and the battery may prevent proper operation. ul recognized to ensure against reverse chargingwhen used with a lithium battery. 21 21 (ds12887a/ ds12c887a) 25 24 rclr active-low ram clear. the rclr pin is used to clear (set to logic 1) all the general-purpose ram, but does not affect the ram associated with the rtc. toclear the ram, rclr must be forced to an input logic 0 during battery-backup mode when v cc is not applied. the rclr function is designed to be used through a human interface (shorting to ground manually or by a switch) and notto be driven with external buffers. this pin is internally pulled up. do not use an external pullup resistor on this pin. 23 23 27 26 sqw square-wave output. the sqw pin can output a signal from one of 13 tapsprovided by the 15 internal divider stages of the rtc. the frequency of the sqw pin can be changed by programming register a, as shown in table 1. the sqw signal can be turned on and off using the sqwe bit in register b. the sqw signal is not available when v cc is less than v pf . 24 24 28 28 v cc dc power pin for primary power supply. when v cc is applied within normal limits, the device is fully accessible and data can be written and read. whenv cc is below v pf reads and writes are inhibited. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ _________________ 11 detailed description the ds12885 family of rtcs provide 14 bytes of real-time clock/calendar, alarm, and control/status registers and 114 bytes (113 bytes for ds12c887 and ds12c887a) of nonvolatile, battery-backed static ram. a time-of-day alarm, three maskable interrupts with a common interrupt output, and a programmable square- wave output are available. the devices also operate in either 24-hour or 12-hour format with an am/pm indica- tor. a precision temperature-compensated circuit moni- tors the status of v cc . if a primary power-supply failure is detected, the devices automatically switch to a back-up supply. the backup supply input supports a primary battery, such as lithium coin cell. the devices are accessed through a multiplexed address/data bus that supports intel and motorola modes. oscillator circuit the ds12885 uses an external 32.768khz crystal. theoscillator circuit does not require any external resistors or capacitors to operate. table 1 specifies several crys- tal parameters for the external crystal. figure 1 shows a functional schematic of the oscillator circuit. an enable bit in the control register controls the oscillator. oscillator startup times are highly dependent upon crystal characteristics, pc board leakage, and layout. high esr and excessive capacitive loads are the major contributors to long startup times. a circuit using a crystal with the recommended characteristics and proper layout usually starts within one second. an external 32.768khz oscillator can also drive the ds12885. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is left unconnected. countdown chain x1 x2 crystal c l 1c l 2 rtc registers ds12885 figure 1. oscillator circuit showing internal bias network parameter symbol min typ max units nominalfrequency f o 32.768 khz seriesresistance esr 50 k loadcapacitance c l 6p f table 1. crystal specifications* * the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for additional specifications. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 12 _________________________________________________ ___________________ clock accuracy the accuracy of the clock is dependent upon the accu-racy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. additional error is added by crystal frequency drift caused by temperature shifts. external circuit noise cou- pled into the oscillator circuit can result in the clock run- ning fast. figure 2 shows a typical pc board layout for isolation of the crystal and oscillator from noise. refer to application note 58: crystal considerations with dallas real-time clocks for more detailed information. clock accuracy for ds12887, ds12887a, ds12c887, ds12c887a only the encapsulated dip modules are trimmed at the fac- tory to an accuracy of ? minute per month at +25?. power-down/power-up considerations the real-time clock continues to operate, and the ram,time, calendar, and alarm memory locations remain nonvolatile regardless of the v cc input level. v bat must remain within the minimum and maximum limits whenv cc is not applied. when v cc is applied and exceeds v pf (power-fail trip point), the device becomes accessi- ble after t rec ?f the oscillator is running and the oscil- lator countdown chain is not in reset (register a). thistime allows the system to stablize after power is applied. if the oscillator is not enabled, the oscillator- enable bit is enabled on power-up, and the device becomes immediately accessible. time, calendar, and alarm locations the time and calendar information is obtained by read-ing the appropriate register bytes. the time, calendar, and alarm are set or initialized by writing the appropri- ate register bytes. invalid time or date entries result in undefined operation. the contents of the 10 time, cal- endar, and alarm bytes can be either binary or binary- coded decimal (bcd) format. the day-of-week register increments at midnight, incre- menting from 1 through 7. the day-of-week register is used by the daylight saving function, so the value 1 is defined as sunday. the date at the end of the month is automatically adjusted for months with fewer than 31days, including correction for leap years. before writing the internal time, calendar, and alarm reg- isters, the set bit in register b should be written to logic 1 to prevent updates from occurring while access is being attempted. in addition to writing the 10 time, calen- dar, and alarm registers in a selected format (binary or bcd), the data mode bit (dm) of register b must be set to the appropriate logic level. all 10 time, calendar, and alarm bytes must use the same data mode. the set bit in register b should be cleared after the data mode bit has been written to allow the rtc to update the time and calendar bytes. once initialized, the rtc makes all updates in the selected mode. the data mode cannot be changed without reinitializing the 10 data bytes. tables 2a and 2b show the bcd and binary formats of the time, calendar, and alarm locations. the 24-12 bit cannot be changed without reinitializing the hour locations. when the 12-hour format is selected, the higher-order bit of the hours byte represents pm when it is logic 1. the time, calendar, and alarm bytes are always accessible because they are double-buffered. once per second the seven bytes are advanced by one second and checked for an alarm condition. if a read of the time and calendar data occurs during an update, a problem exists where seconds, minutes, hours, etc., may not correlate. the probability of read- ing incorrect time and calendar data is low. several methods of avoiding any possible incorrect time and calendar reads are covered later in this text. local ground plane (top layer) crystal gnd x2 x1 note: avoid routing signal lines in the crosshatched area (upper left quadrant) of the package unless there is a ground plane between the signal line and the device package. figure 2. layout example downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ _________________ 13 the three alarm bytes can be used in two ways. first,when the alarm time is written in the appropriate hours, minutes, and seconds alarm locations, the alarm inter- rupt is initiated at the specified time each day, if the alarm-enable bit is high. in this mode, the ??bits in the alarm registers and the corresponding time registers must always be written to 0 (table 2a and 2b). writing the 0 bits in the alarm and/or time registers to 1 can result in undefined operation. the second use condition is to insert a ?on? care state in one or more of the three alarm bytes. the don?- care code is any hexadecimal value from c0 to ff. the two most significant bits of each byte set the don?-care condition when at logic 1. an alarm is generated eachhour when the don?-care bits are set in the hours byte. similarly, an alarm is generated every minute with don?-care codes in the hours and minute alarm bytes. the don?-care codes in all three alarm bytes create an interrupt every second. all 128 bytes can be directly written or read, except for the following: 1) registers c and d are read-only. 2) bit 7 of register a is read-only. 3) the msb of the seconds byte is read-only. table 2a. time, calendar, and alarm data modesbcd mode (dm = 0) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00?9 01h 0 10 seconds seconds seconds alarm 00?9 02h 0 10 minutes minutes minutes 00?9 03h 0 10 minutes minutes minutes alarm 00?9 am/pm 0 10 hours 04h 0 0 10 hours hours hours 1?2 +am/pm 00?3 am/pm 0 10 hours 05h 0 0 10 hours hours hours alarm 1?2 +am/pm 00?3 06h 0 0 0 0 0 day day 01?7 07h 0 0 10 date date date 01?1 08h 0 0 0 10 months month month 01?2 09h 10 years year year 00?9 0ah uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 control 0bh set pie aie uie sqwe dm 24/12 dse control 0ch irqf pf af uf 0 0 0 0 control 0dh vrt 0 0 0 0 0 0 0 control 0eh-31h x x x x x x x x ram 32h 10 century century century* 00?9 33h-7fh x x x x x x x x ram x = read/write bit. * ds12c887, ds12c887a only. general-purpose ram on ds12885, ds12887, and ds12887a. note: unless otherwise specified, the state of the registers is not defined when power is first applied. except for the seconds regis - ter, 0 bits in the time and date registers can be written to 1, but may be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 14 _________________________________________________ ___________________ table 2b. time, calendar, and alarm data modesbinary mode (dm = 1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 0 seconds seconds 00?b 01h 0 0 seconds seconds alarm 00?b 02h 0 0 minutes minutes 00?b 03h 0 0 minutes minutes alarm 00?b am/pm 0 hours 04h 0 00 hours hours 01?c +am/pm 00?7 am/pm 0 hours 05h 0 0 0 hours hours alarm 01?c +am/pm 00?7 06h 0 0 0 0 0 day day 01?7 07h 0 0 0 date date 01?f 08h 0 0 0 0 month month 01?c 09h 0 year year 00?3 0ah uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 control 0bh set pie aie uie sqwe dm 24/12 dse control 0ch irqf pf af uf 0 0 0 0 control 0dh vrt 0 0 0 0 0 0 0 control 0eh-31h x x x x x x x x ram 32h n/a n/a century* 33h-7fh x x x x x x x x ram x = read/write bit. * ds12c887, ds12c887a only. general-purpose ram on ds12885, ds12887, and ds12887a. note: unless otherwise specified, the state of the registers is not defined when power is first applied. except for the seconds regis - ter, 0 bits in the time and date registers can be written to 1, but may be modified when the clock updates. 0 bits should always be written to 0 except for alarm mask bits. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ _________________ 15 bit 7: update-in-progress (uip). this bit is a status flag that can be monitored. when the uip bit is a 1, theupdate transfer occurs soon. when uip is a 0, the update transfer does not occur for at least 244?. the time, calendar, and alarm information in ram is fully available for access when the uip bit is 0. the uip bit is read-only and is not affected by reset . writing the set bit in register b to a 1 inhibits any update transferand clears the uip status bit. bits 6, 5, and 4: dv2, dv1, dv0. these three bits are used to turn the oscillator on or off and to reset thecountdown chain. a pattern of 010 is the only combina- tion of bits that turn the oscillator on and allow the rtc to keep time. a pattern of 11x enables the oscillator but holds the countdown chain in reset. the next update occurs at 500ms after a pattern of 010 is written to dv0, dv1, and dv2. bits 3 to 0: rate selector (rs3, rs2, rs1, rs0). these four rate-selection bits select one of the 13 taps on the 15-stage divider or disable the divider output. the tap selected can be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the user can do one of the following: 1) enable the interrupt with the pie bit; 2) enable the sqw output pin with the sqwe bit; 3) enable both at the same time and the same rate; or 4) enable neither. table 3 lists the periodic interrupt rates and the square- wave frequencies that can be chosen with the rs bits. these four read/write bits are not affected by reset . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uip dv2 dv1 dv0 rs3 rs2 rs1 rs0 control register a control registers the real-time clocks have four control registers that areaccessible at all times, even during the update cycle. msb lsb downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 16 _________________________________________________ ___________________ bit 7: set. when the set bit is 0, the update transfer functions normally by advancing the counts once persecond. when the set bit is written to 1, any update transfer is inhibited, and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. read cycles can be executed in a similar manner. set is a read/write bit and is not affected by reset or internal functions of the device. bit 6: periodic interrupt enable (pie). the pie bit is a read/write bit that allows the periodic interrupt flag (pf) bitin register c to drive the irq pin low. when the pie bit is set to 1, periodic interrupts are generated by driving theirq pin low at a rate specified by the rs3?s0 bits of register a. a 0 in the pie bit blocks the irq output from being driven by a periodic interrupt, but the pf bit is stillset at the periodic rate. pie is not modified by any internal device functions, but is cleared to 0 on reset . bit 5: alarm interrupt enable (aie). this bit is a read/write bit that, when set to 1, permits the alarm flag(af) bit in register c to assert irq . an alarm interrupt occurs for each second that the three time bytes equalthe three alarm bytes, including a don?-care alarm code of binary 11xxxxxx. the af bit does not initiate the irq signal when the aie bit is set to 0. the internal functions of the device do not affect the aie bit, but iscleared to 0 on reset . bit 4: update-ended interrupt enable (uie). this bit is a read/write bit that enables the update-end flag (uf)bit in register c to assert irq . the reset pin going low or the set bit going high clears the uie bit. the internal functions of the device do not affect the uie bit, but is cleared to 0 on reset . bit 3: square-wave enable (sqwe). when this bit is set to 1, a square-wave signal at the frequency set bythe rate-selection bits rs3?s0 is driven out on the sqw pin. when the sqwe bit is set to 0, the sqw pin is held low. sqwe is a read/write bit and is cleared by reset . sqwe is low if disabled, and is high impedance whenv cc is below v pf . sqwe is cleared to 0 on reset . bit 2: data mode (dm). this bit indicates whether time and calendar information is in binary or bcd format.the dm bit is set by the program to the appropriate for- mat and can be read as required. this bit is not modi- fied by internal functions or reset . a 1 in dm signifies binary data, while a 0 in dm specifies bcd data. bit 1: 24/12. the 24/12 control bit establishes the for- mat of the hours byte. a 1 indicates the 24-hour modeand a 0 indicates the 12-hour mode. this bit is read/write and is not affected by internal functions or reset . bit 0: daylight saving enable (dse). this bit is a read/write bit that enables two daylight saving adjust-ments when dse is set to 1. on the first sunday in april, the time increments from 1:59:59 am to 3:00:00 am. on the last sunday in october when the time first reaches 1:59:59 am, it changes to 1:00:00 am. when dse is enabled, the internal logic test for the first/last sunday condition at midnight. if the dse bit is not set when the test occurs, the daylight saving function does not operate correctly. these adjustments do not occur when the dse bit is 0. this bit is not affected by internal functions or reset . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set pie aie uie sqwe dm 24/12 dse control register b msb lsb downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ _________________ 17 bit 7: interrupt request flag (irqf). this bit is set to 1 when any of the following are true: pf = pie = 1af = aie = 1 uf = uie = 1 any time the irqf bit is 1, the irq pin is driven low. this bit can be cleared by reading register c or with areset . bit 6: periodic interrupt flag (pf). this bit is read- only and is set to 1 when an edge is detected on theselected tap of the divider chain. the rs3 through rs0 bits establish the periodic rate. pf is set to 1 indepen- dent of the state of the pie bit. when both pf and pie are 1s, the irq signal is active and sets the irqf bit. this bit can be cleared by reading register c or with areset . bit 5: alarm interrupt flag (af). a 1 in the af bit indi- cates that the current time has matched the alarm time.if the aie bit is also 1, the irq pin goes low and a 1 appears in the irqf bit. this bit can be cleared byreading register c or with a reset . bit 5: update-ended interrupt flag (uf). this bit is set after each update cycle. when the uie bit is set to1, the 1 in uf causes the irqf bit to be a 1, which asserts the irq pin. this bit can be cleared by reading register c or with a reset . bits 3 to 0: unused. these bits are unused in register c. these bits always read 0 and cannot be written. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irqf pf af uf 0 0 0 0 control register c bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v r t0000000 control register d bit 7: valid ram and time (vrt). this bit indicates the condition of the battery connected to the v bat pin. this bit is not writeable and should always be 1 whenread. if a 0 is ever present, an exhausted internal lithi- um energy source is indicated and both the contents of the rtc data and ram data are questionable. this bitis unaffected by reset . bits 6 to 0: unused. the remaining bits of register d are not usable. they cannot be written and they alwaysread 0. msb lsb msb lsb downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 18 _________________________________________________ ___________________ century register (ds12c887/ds12c887a only) the century register at location 32h is a bcd registerdesigned to automatically load the bcd value 20 as the year register changes from 99 to 00. the msb of this register is not affected when the load of 20 occurs, and remains at the value written by the user. nonvolatile ram (nv ram) the general-purpose nv ram bytes are not dedicatedto any special function within the device. they can be used by the processor program as battery-backed memory and are fully available during the update cycle. interrupts the rtc family includes three separate, fully automaticsources of interrupt for a processor. the alarm interrupt can be programmed to occur at rates from once per second to once per day. the periodic interrupt can be selected for rates from 500ms to 122?. the update- ended interrupt can be used to indicate to the program that an update cycle is complete. each of these inde- pendent interrupt conditions is described in greater detail in other sections of this text. the processor program can select which interrupts, if any, are to be used. three bits in register b enable the interrupts. writing a logic 1 to an interrupt-enable bit permits that interrupt to be initiated when the event occurs. a 0 in an interrupt-enable bit prohibits the irq pin from being asserted from that interrupt condition. ifan interrupt flag is already set when an interrupt is enabled, irq is immediately set at an active level, although the interrupt initiating the event may haveoccurred earlier. as a result, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. when an interrupt event occurs, the relating flag bit is set to logic 1 in register c. these flag bits are set inde- pendent of the state of the corresponding enable bit in register b. the flag bit can be used in a polling mode without enabling the corresponding enable bits. the interrupt flag bit is a status bit that software can interro- gate as necessary. when a flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read; however, care should be taken when using the flag bits as they are cleared each time register c is read. double latching is includ- ed with register c so that bits that are set remain sta- ble throughout the read cycle. all bits that are set (high) are cleared when read, and new interrupts that are pending during the read cycle are held until after the cycle is completed. one, two, or three bits can be set when reading register c. each used flag bit should beexamined when register c is read to ensure that no interrupts are lost. the second flag bit method is used with fully enabled interrupts. when an interrupt flag bit is set and the cor- responding interrupt-enable bit is also set, the irq pin is asserted low. irq is asserted as long as at least one of the three interrupt sources has its flag and enable bitsset. the irqf bit in register c is a 1 whenever the irq pin is driven low. determination that the rtc initiated aninterrupt is accomplished by reading register c. a logic 1 in bit 7 (irqf bit) indicates that one or more interrupts have been initiated by the device. the act of reading register c clears all active flag bits and the irqf bit. oscillator control bits when the ds12887, ds12887a, ds12c887, andds12c887a are shipped from the factory, the internal oscillator is turned off. this prevents the lithium energy cell from being used until the device is installed in a system. a pattern of 010 in bits 4 to 6 of register a turns the oscillator on and enables the countdown chain. a pat- tern of 11x (dv2 = 1, dv1 = 1, dv0 = x) turns the oscil- lator on, but holds the countdown chain of the oscillator in reset. all other combinations of bits 4 to 6 keep the oscillator off. square-wave output selection thirteen of the 15 divider taps are made available to a 1-of-16 multiplexer, as shown in the functional diagram. the square-wave and periodic-interrupt generators share the output of the multiplexer. the rs0?s3 bits in register a establish the output frequency of the multi- plexer (see table 1). once the frequency is selected, the output of the sqw pin can be turned on and off under program control with the square-wave enable bit, sqwe. periodic interrupt selection the periodic interrupt causes the irq pin to go to an active state from once every 500ms to once every 122?.this function is separate from the alarm interrupt, which can be output from once per second to once per day. the periodic interrupt rate is selected using the same register a bits that select the square-wave frequency (table 1). changing the register a bits affects the square-wave frequency and the periodic-interrupt out- put. however, each function has a separate enable bit in register b. the sqwe bit controls the square-wave out- put. similarly, the pie bit in register b enables the peri- odic interrupt. the periodic interrupt can be used with software counters to measure inputs, create output inter- vals, or await the next needed software function. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ _________________ 19 update cycle the device executes an update cycle once per secondregardless of the set bit in register b. when the set bit in register b is set to 1, the user copy of the double- buffered time, calendar, and alarm bytes is frozen and does not update as the time increments. however, the time countdown chain continues to update the internal copy of the buffer. this feature allows time to maintain accuracy independent of reading or writing the time, calendar, and alarm buffers, and also guarantees that time and calendar information is consistent. the update cycle also compares each alarm byte with the corre- sponding time byte and issues an alarm if a match or ifa don?-care code is present in all three positions. there are three methods that can handle rtc access that avoid any possibility of accessing inconsistent time and calendar data. the first method uses the update- ended interrupt. if enabled, an interrupt occurs after every update cycle that indicates over 999ms is avail- able to read valid time and date information. if this interrupt is used, the irqf bit in register c should be cleared before leaving the interrupt routine. a second method uses the update-in-progress bit (uip) in register a to determine if the update cycle is in progress. the uip bit pulses once per second. after the uip bit goes high, the update transfer occurs 244? later. if a low is read on the uip bit, the user has at least 244? before the time/calendar data is changed. therefore, the user should avoid interrupt service rou- tines that would cause the time needed to read valid time/calendar data to exceed 244?. the third method uses a periodic interrupt to determine if an update cycle is in progress. the uip bit in register a is set high between the setting of the pf bit in register c (figure 3). periodic interrupts that occur at a rate greater than t buc allow valid time and date information to be reached at each occurrence of the periodic interrupt.the reads should be complete within one (t pi/2 + t buc ) to ensure that data is not read during the update cycle. handling, pc board layout, and assembly the edip module can be successfully processedthrough conventional wave-soldering techniques so long as temperature exposure to the lithium energy source does not exceed +85?. post-solder cleaning with water- washing techniques is acceptable, provided that ultra- sonic vibration is not used. such cleaning can damage the crystal. select bits register a rs3 rs2 rs1 rs0 t pi periodic interrupt rate sqw output frequency 0 0 0 0 none none 0 0 0 1 3.90625ms 256hz 0 0 1 0 7.8125ms 128hz 0 0 1 1 122.070? 8.192khz 0 1 0 0 244.141? 4.096khz 0 1 0 1 488.281? 2.048khz 0 1 1 0 976.5625? 1.024khz 0 1 1 1 1.953125ms 512hz 1 0 0 0 3.90625ms 256hz 1 0 0 1 7.8125ms 128hz 1 0 1 0 15.625ms 64hz 1 0 1 1 31.25ms 32hz 1 1 0 0 62.5ms 16hz 1 1 0 1 125ms 8hz 1 1 1 0 250ms 4hz 1 1 1 1 500ms 2hz table 3. periodic interrupt rate and square-wave output frequency uip uf pf t buc = delay time before update cycle = 244 s 1 second t pi t p1/2 t p1/2 t buc figure 3. uip and periodic interrupt timing downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks 20 _________________________________________________ ___________________ 2423 22 21 20 19 18 17 12 3 4 5 6 7 8 v cc sqwn.c. rclr ad0 x2 x1 mot top view v bat irqreset ds ad4 ad3 ad2 ad1 1615 14 13 9 1011 12 gndr/w as cs gnd ad7 ad6 ad5 so, pdip plcc ds12885 ds12885s ds12885q v cc sqwn.c. n.c. (rclr) ad0 n.c. n.c. mot n.c.irq reset ds ad4 ad3 ad2 ad1 n.c.r/w as cs ( ) for the ds12887a/ds12c887a. note: the ds12887a and ds12c887a cannot be stored or shipped in conductive material that will give a continuity path between the ram clear pin and ground. gnd ad7 ad6 ad5 edip ds12887 ds12887a ds12c887 ds12c887a 12 13 14 15 16 17 18 1 n.c. v cc sqw n.c. mot x1 x2 gnd cs as n.c.ad7 n.c. ad6 23 4 2627 28 19 20 21 22 23 24 25 56 7 8 9 10 11 ad0ad1 ad2 ad3 ad4 ad5 n.c. rclrv bat irqreset ds gnd r/w 12 3 4 5 6 7 8 9 1011 12 2423 22 21 20 19 18 17 1615 14 13 pin configurations downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks ___________________________________________________ _________________ 21 package theta-ja (?/w) theta-jc (?/w) pdip 75 30 so 105 22 plcc 95 25 thermal information chip information process: cmossubstrate connected to ground tqfp top view 32 28 29 30 31 25 26 27 x2x1 mot v cc n.c.n.c. sqw n.c. 10 13 15 14 16 11 12 9 ad6ad7 n.c. cs gnd n.c. as r/w 17 18 19 20 21 22 23 n.c. 24 rclr v bat irq n.c.reset ds gnd 2 3 4 5 6 7 8 ad5 ad4 n.c. ad3 n.c. ad2 ad1 1 ad0 ds12885t pin configurations (continued) ordering information part temp range pin-package top mark* ds12885 + 0c to +70c 24 pdip ds12885 ds12885n+ -40c to +85c 24 pdip ds12885 ds12885q+ 0c to +70c 28 plcc ds12885q ds12885qn+ -40c to +85c 28 plcc ds12885q ds12885q+t&r 0c to +70c 28 plcc ds12885q ds12885qn+t&r -40c to +85c 28 plcc ds12885q ds12885s+ 0c to +70c 24 so (300 mils) ds12885s ds12885sn+ -40c to +85c 24 so (300 mils) ds12885s ds12885s+t&r 0c to +70c 24 so (300 mils) ds12885s ds12885t+ 0c to +70c 32 tqfp ds12885 DS12885TN+ -40c to +85c 32 tqfp ds12885 ds12887 + 0c to +70c 24 edip ds12887 ds12887a + 0c to +70c 24 edip ds12887a ds12c887 + 0c to +70c 24 edip ds12c887 ds12c887a + 0c to +70c 24 edip ds12c887aa + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. *a ??anywhere on the top mark indicates a lead(pb)-free device, and an ??indicates an industrial temperature range device. package type package code document no. 24 so w24+1 21-0042 24 pdip p24+4 21-0044 24 edip mdp24+1 21-0241 28 plcc q28+13 21-0049 32 tqfp c32+3 21-0292 package information for the latest package outline information and land patterns,go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
ds12885/ds12887/ds12887a/ds12c887/ds12c887a real-time clocks maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. is a registered trademark of maxim integrated products, inc. quijano revision history revision number revision date description pages changed 0 6/05 initial release of combined data sheet 1 4/06 corrected the intel bus write timing , intel bus read timing , irq release dela timing , power-up/down timing , and functional diagram diagrams; added the handling, pc board laout , and assembl section. 4, 5, 7, 20 2 5/06 corrected the intel bus write timing diagram; added plcc pin description information; changed pin 16 from n.c. to gnd for the so and pdip packages. 4, 8, 9, 10, 20 3 2/07 corrected the intel bus write timing diagram; updated the ordering information ; added the package information table; removed the package drawings. 4, 20, 22C27 4 4/10 updated the storage temperature ranges, added the lead temperature, and updated the soldering temperature for all packages in the absolute maximum ratings ; removed leaded parts from the ordering information table. 2, 21 downloaded from: http:///

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